Important Dates

20th January 2017
Notification of
04th March 2017
24th March 2017
Conference dates: 19th to 21th April 2017

Technical Program DDECS2017
Wednesday, April 19

13:30 - 14:00Kurfürstensaal A
DDECS Welcome
Manfred Dietrich, Ondřej Novák
14:00 - 15:00Chair: Manfred Dietrich Kurfürstensaal A
Session I - Keynote Presentation
FDSOI – New circuit architectures for Low Power Embedded Designs
15:05 - 16:05Chair: György Cserey Kurfürstensaal A
Poster Session - II
Saurabh Chaturvedi, Mladen Božanić, Saurabh Sinha:
A 50 GHz SiGe BiCMOS Active Bandpass Filter

Andreas Rauchenecker, Robert Wille:
An Efficient Physical Design of Fully-testable BDD-based Circuits

Tohid Taghizad Gogjeh Yaran, Suleyman Tosun:
Improving Combinational Circuit Resilience against Soft Errors via Selective Resource Allocation

Matej Rakús, Viera Stopjaková, Daniel Arbet:
Analysis of Bulk-Driven and Dynamic-Threshold Current Mirrors for Low-Voltage Applications

Tino Flenker, Görschwin Fey:
Mapping Abstract and Concrete Hardware Models for Design Understanding

Mustafa Özgül, Florian Deeg, Sebastian M. Sattler:
Mealy-to-Moore Transformation

Imran Wali, Marcello Traiola, Arnaud Virazel, Patrick Girard, Mario Barbareschi, Alberto Bosio:
Towards Approximation during Test of Integrated Circuits

Farnoosh Hosseinzadeh, Petr Pfeifer, Heinrich Theodor Vierhaus:
On Error Resilience Techniques for FPGA-based Processors

16:05 - 16:35Coffee Break
16:35 - 18:35Chair: Hans-Joachim Wunderlich Kurfürstensaal AChair: Viera Stopjaková Kurfürstensaal B
Session III – Test and Verification
Matthias Kampmann, Sybille Hellebrand:
Design-for-FAST: Supporting X-tolerant Compaction during Faster-than-at-Speed Test

Davide Dicorato, Petr Pfeifer, Heinrich T. Vierhaus:
Fault Detection and Self Repair in Hsiao-Code FEC Circuits

Siavoosh Payandeh Azad, Behrad Niazmand, Karl Janson, Nevin George, Tsotne Putkaradze, Adeboye Stephen Oyeniran, Apneet Kaur, Jaan Raik, Gert Jervan, Raimund Ubar, Thomas Hollstein:
From Online Fault Detection to Fault Management in Network-on-Chips: A Ground-up Approach

Ondrej Novak, Zdenek Pliva:
Logic Testing with Test-per-Clock Pattern Loading and Improved Diagnostic Abilities
Session IV – Analog and RF Design
Marko Andjelkovic, Milos Krstic, Rolf Kraemer:
An Analysis of the Operation and SET Robustness of a CMOS Pulse Stretching Circuit

Paweł Narczyk, Krzysztof Siwiec, Witold A. Pleskacz:
Analog Front-End for Precise Human Body Temperature Measurement

Sunil Satish Rao, Benjamin Prautsch, Ashish Shrivastava, Torsten Reich:
Body Biasing for Analog Design: Practical Experiences in 22 nm FD-SOI

Michal Wolodzko, Wieslaw Kuzmicz:
A Low Power Input Amplifier for Bio-Signal Acquisition in 28 nm FDSOI Technology
Welcome Party

Thursday, April 20

9:00-10:00Chair: Peter Schneider Kurfürstensaal A
Session V- Keynote Presentation
Hans-Joachim Wunderlich:
50 years of self-test: From random patterns to in-field automotive testing and health monitoring
10:00–10:30Coffee Break
10:30 - 12:00Chair: Alberto Bosio Kurfürstensaal AChair: Marcela Zachariasova Kurfürstensaal B
Session VI - System Design
Arash Barzinmehr, Suleyman Tosun:
Energy-Aware Application-Specific Topology Generation for 3D Network-on-Chips

Ondrej Kachman, Marcel Balaz
Firmware Update Manager: A Remote Firmware Reprogramming Tool for Low-Power Devices

Madis Kerner, Kalle Tammemäe:
Hierarchical Temporal Memory implementation on FPGA using LFSR based spatial pooler address space generator
Session VII - Modelling
Michael Schwarz, Dominik Stoffel, Wolfgang Kunz:
Cycle-Accurate Software Modeling for RTL Verification of Embedded Systems

Andreas Fürtig, Georg Gläser, Christoph Grimm, Lars Hedrich, Stefan Heinen, Hyun-Sek Lukas Lee, Gregor Nitsche, Markus Olbrich, Carna Radojicic, Fabian Speicher:
Novel Metrics for Analog Mixed-Signal Coverage

Feim Ridvan Rasim, Canan Kocar, Sebastian M. Sattler:
Structure-Preserving Modeling of Safety-Critical Combinational Circuits
12:00 - 13:00Lunch
13:00 - 14:30Chair: Witold A. Pleskacz Kurfürstensaal AChair: Sybille Hellebrand Kurfürstensaal B
Session VIII – Analog and RF Design
Thomas Polzer, Florian Huemer, Andreas Steininger:
Measuring Metastability Using a Time-to-Digital Converter

Oliver Schrape, Manuel Herrmann, Frank Winkler, Milos Krstic:
Routing Approach for Digital, Differential Bipolar Designs using Virtual Fat-Wire Boundary Pins

Michal Sovcik, Martin Kovac, Daniel Arbet, Viera Stopjakova:
Ultra-Low Voltage Driver for Large Load Capacitance in 130nm CMOS
Session IX – Synthesis
Ivo Halecek, Petr Fiser, Jan Schmidt:
Are XORs in logic synthesis really necessary?

Marcello Traiola, Mario Barbareschi, Alberto Bosio:
Formal Design Space Exploration for Memristor-based Crossbar Architecture

Miroslav Siro, Dominik Macko, Katarína Jelemenská:
PMS2UPF: An Automated Transition from ESL to RTL Power-Intent Specification
14:30 - 16:00Poster exhibition (coffee Break)
16:00 - 17:00Chair: Peter Fišer Kurfürstensaal AChair: Sebastian Sattler Kurfürstensaal B
Session X – Digital Design
Raimund Ubar, Sergei Kostin, Maksim Jenihhin, Jaan Raik:
A Scalable Technique to Identify True Critical Paths in Sequential Circuits

Lei Xie, Hoang Anh Du Nguyen, Jintao Yu, Mottaqiallah Taouil, Said Hamdioui:
On the Robustness of Memristor Based Logic Gates
Session XI – Industrial
Norbert Druml, Christoph Ehrenhoefer, Walter Bell, Christian Gailer, Hannes Plank, Thomas Herndl, and Gerald Holweg:
A fast and flexible HW/SW co-processing framework for Time-of-Flight 3D imaging

Radek Iša, Jiří Matoušek:
A Novel Architecture for LZSS Compression of Configuration Bitstreams Within FPGA

17:10 - 18:10Chair: Karel Vlček Kurfürstensaal AChair: Lars HedrichKurfürstensaal B
Session XII – Embedded tutorial
Zdenek Vasicek:
Relaxed equivalence checking: a new challenge in logic synthesis
Session XIII – Embedded tutorial
Goran Stojanovic, Zoran Stamenković:
Sensors and Electronic Systems for Agricultural and Environmental Monitoring
19:00Social Event

Friday, April 21

9:00-10:00Chair: Zoran Stamenković Kurfürstensaal A
Session XIV- Keynote Presentation
Dirk Droste, Bosch Sensortec:
IoT and MEMS Sensor ASICs - how the classical development approach will have to change
10:00–10:30Coffee Break
10:30 - 12:00Chair: Katarina JelemenskáKurfürstensaal AChair: Heinrich T. Vierhaus Kurfürstensaal B
Session XV - Security and Applications
Asma Mkhinini, Paolo Maistri, Regis Leveugle, Rached Tourki:
HLS Design of a Hardware Accelerator for Homomorphic Encryption

Petr Socha, Vojtěch Miškovský, Hana Kubátová, Martin Novotný:
Optimization of Pearson correlation coefficient calculation for DPA and comparison of different approaches

Saya Ohira, Tetsuya Matsumura:
Design for Three-Dimensional Sound Processor using High-Level Synthesis
Session XVI - System Design
Patrick Russell, Jens Döge, Christoph Hoppe, Thomas B. Preußer, Peter Reichel, Peter Schneider:
Implementation of an Asynchronous Bundled-Data Router for a GALS NoC in the Context of a VSoC

Felix Mühlbauer, Lukas Schröder, Mario Schölzel:
On Hardware-based Fault-Handling in Dynamically Scheduled Processors

Lukas Kohutka, Viera Stopjakova:
Rocket Queue: New Data Sorting Architecture for Real-Time Systems
12:00 - 12:30Kurfürstensaal A
Closing Session
12:30 - 13:30Lunch

Fraunhofer IIS/EAS


Fraunhofer IIS/EAS

Fraunhofer-Institute for Integrated Circuits IIS, Division Engineering of Adaptive Systems EAS


Technically 	Co-Sponsored by the IEEE Computer Society

Technically 	Co-Sponsored by Cadence

Technically 	Co-Sponsored by BOSCH Sensortec